A team of electrical and computer engineering professors, including two of Indian origin, from the University of California, Los Angeles, has received a $5.9 million research grant from the U.S. Department of Defense to develop energy-efficient computing systems that can process massive amounts of data at speeds much faster than currently possible.
Professors Sudhakar Pamarti, Puneet Gupta and Kang Wang, experts in nanotechnology, computing systems, design automation and integrated circuit design, are working on a project to address what is called the “memory bottleneck,” where computing speeds go down as information is shuttled between memory and processing chips.
The grant is from the Defense Advanced Research Projects Agency, or DARPA, and is part of a larger effort, called the Electronics Resurgence Initiative, to solve fundamental challenges in computing and microelectronics to help continue Moore’s Law – which has successfully predicted the continual shrinking of transistors for microelectronics over the past five decades, according to the March 19, press release from the UCLA Samueli School of Engineering and Applied Science.
“As computers are required to handle larger and larger amounts of data, the energy required to process that information has become a limiting factor in computing speed,” noted an April 8 press release from UCLA.
According to the UCLA Samueli School of Engineering, through this “revolutionary technology” called Spintronic Stochastic Dataflow Computing, the research team aims to demonstrate a reduction in energy use of 60 times less than current technologies in data-intensive computer tasks such as machine learning.
Parmarti, a graduate of the Indian Institute of Technology, Kharagpur, and a Ph.D. in electrical engineering from UC San Diego, is associate professor and area director, Circuits & Embedded Systems at UCLA School of Electrical and Computer Engineering.
Before he joined UCLA in 2005, Parmarti worked with Rambus Inc. (2003-2005) where he designed mixed-signal circuits for high speed electrical interfaces for communication between multiple integrated circuits (ICs). He has also worked with Hughes Software Systems (1995-1997) developing real-time, embedded software and firmware for a wireless-in-local-loop communication system, according to information on the UCLA website.
Kang Wang holds UCLA’s Raytheon Chair of Electrical and Computer Engineering.
“It used to be that processing speeds were the main hurdles to computing performance, but as those have improved, that progress has been outpaced by the arrival of big data,” Pamarti is quoted saying in the March 19 press release. “The paradigm has been flipped and the processors can’t handle all this data without using a lot of energy for moving it around.”
Parmarti describes the memory bottleneck as “arguably the biggest challenge for the design of new computing systems,” and notes that his team is developing an innovative two-part approach to work around that issue.
The first part involves deploying a type of computer memory technology that uses dramatically less energy than current technologies, called “MeRAM.” This offers the best reported combination of energy, speed, and density among existing and emerging non-volatile memory technologies, these researchers believe.
The second part is “stochastic computing” which requires very compact hardware that work in parallel with each other, relaxing the memory bottleneck problem, they say. In addition, stochastic computing makes computations progressively more accurate, making it possible to tune the devices to trade off their energy consumption for approximate answers when those will suffice. Add to that the fact that the two technologies will work very well together, the researchers say.